LIST OF VLSI COMPANIES

Company	Website	Type	Location
Achronix Semiconductor Corp	www.achronix.com	Product	Bangalore
Adept Chips	www.adeptchips.com	Services	Bangalore
Adi Semiconductor	startup	Services	Bangalore
Aizyc Technology	www.aizyc.com	Services	Hyderabad
Altera Semiconductor Pvt Ltd.	www.altera.com	Product	Bangalore
AMD	www.amd.com	Product	Bangalore/ Hyderabad
Analog Devices	www.analog.com	Product	Bangalore
Apache Design Solutions	www.apache-da.com	Product	Bangalore
Applied Materials	www.appliedmaterials.com	Product	Bangalore
Applied micro Circuits	www.apm.com	Product	Bangalore
Aptina India Pvt Ltd.	www.aptina.com	Product	Bangalore
Arasan Chip Systems Inc.	www.arasan.com	Product	Bangalore
ARM	www.arm.com	Product	Bangalore
Arrow Devices	www.arrowdevices.com	Services	Bangalore
Atmel Corporation	www.atmel.in	Product	Bangalore
Atoptech	www.atoptech.com	Product	Bangalore
Atrenta	www.atrenta.com	Product	Noida
Aura Semiconductor	www.aurasemi.com	Services	Bangalore
Berkeley DA	www.berkeley-da.com	Product	Bangalore
Black Pepper Technologies	www.blackpeppertech.com	Services	Bangalore
Broadcom	www.broadcom.com	Product	Bangalore
Cadence Design Systems	www.cadence.com	Product	Bangalore/ Noida
Calypto Design Systems	www.calypto.com	Product	Bangalore
Cavium Networks	www.cavium.com	Product	Bangalore
Chelsio Communications	www.chelsio.com	Product	Bangalore
CircuitSutra	www.circuitsutra.com	Product	Bangalore
Cognitive Design Technology Pvt Ltd	www.cognitivetech.co.in	Product	Bangalore
Concept2silicon	www.concept2silicon.com	Service	Bangalore
Conexant Systems	www.conexant.com		Bangalore
Connexion Semiconductors Pvt. Ltd.	http://connexionsemiconductor.com	Services	Bangalore
Cortina Systems	www.cortina-systems.com	Product	Bangalore
Cosmic Circuits	www.cosmiccircuits.com	Product	Bangalore
Cypress Semiconductor	www.cypress.com	Product	Bangalore
DXCorr	www.dxcorr.com	Product	Bangalore
eInfochips	www.einfochips.com	Services	Ahemdabad/ Bangalore
esilicon	www.esilicon.com	Services	Bangalore
ELVEEGO CIRCUITS	www.elveegocircuits.com	Services	Bangalore
First Pass Semiconductor	www.firstpass-semi.com	Services	Bangalore
Freescale Semiconductor	www.freescale.com	Product	Noida/ Bangalore
Four Arrow Systems and Technologies Pvt Ltd		Services	Bangalore
IBM	www.ibm.com/in/en	Services	Bangalore
ICON Design Automation	www.icon-dapl.com		Bangalore
Ikanos Communications	www.ikanos.com	Product	Bangalore
iKoa Semiconductor India Pvt. Ltd.			Bangalore
Infosys	www.infosys.com	Services	Bangalore
Infineon Technologies	www.infineon.com	Product	Bangalore
Infotech Enterprise	www.infotech-enterprises.com	Services	Bangalore
Intel Corporation	www.intel.com	Product	Bangalore
Interra systems	www.interrasystems.com		Bangalore
Intresil Semiconductor	www.intersil.com		Bangalore
Ittiam	www.ittiam.com		Bangalore
Juniper Networks	www.juniper.net	Product	Bangalore
Kacper Technologies Pvt Ltd	www.kacpertech.com		Bangalore
Karnataka Microelectronic Design Centre	www.karmic.co.in		Bangalore
Kasura Technologies...	www.kasura.com	Product	Bangalore
Kawasaki Microelectronics	www.k-micro.us		Bangalore
KPIT Cummins Infosystems Limited	www.kpitcummins.com	Services	Bangalore
lattice Semiconductor	www.latticesemi.com	Product	Bangalore
Logic Fab	www.logicfab.com	Services	Bangalore
LSI Corporation	www.lsi.com	Product	Bangalore
Magma Deisgn Automation	www.synopsys.com	EDA	Bangalore
Mandate Chips and Circuits Pvt. Ltd.	www.mandatecc.com	Product	Bangalore
Manthan Semiconductors Pvt Ltd/		Services	Bangalore
Marvell Semiconductor	www.marvell.com	Product	Bangalore
Masamb Electronics Systems	www.masamb.com	Services	Noida
Maxim Integrated	www.maximintegrated.com	Product	Bangalore
MaxLinear	www.maxlinear.com	Product	Bangalore
MediaTek	www.mediatek.com	Product	Noida
Mentor Graphics	www.mentor.com	EDA	Bangalore/ Noida
Microchip Technology	www.microchip.com	Product	Bangalore
Micron Tech	www.micron.com		Bangalore
Microsemi	www.microsemi.com	Product	Hyderabad
Millennium Semiconductors	www.millenniumsemi.com		Bangalore
Mindtree Ltd.	www.mindtree.com		Bangalore
Mirafra Technologies	www.mirafra.com	Services	Bangalore
Mistral	www.mistralsolutions.com		Bangalore
Moschip Semiconductor	www.moschip.com		Bangalore
Moslogi Technologies	www.moslogi.com		Bangalore
MoSys	www.mosys.com		Bangalore
National Semiconductor	www.ti.com	Product	Bangalore
NEC Electronics	www.nec.com		Bangalore
NetLogic Microsystems	www.broadcom.com	Product	Bangalore
nSys Design Systems	www.synopsys.com	Product	Bangalore
NV Logic	www.nvlogic.com	Services	Hyderabad
NVIDIA	www.nvidia.com	Product	Bangalore
NXP Semiconductor	www.nxp.com	Product	Bangalore
ON Semiconducor	www.onsemi.com	Product	Bangalore
OpenSilicon	www.open-silicon.com		Bangalore
Perfect Vips	www.perfectvips.com	Product	Bangalore
Perfectus	www.perfectus.com	Product	Bangalore
PLX Technology	www.plxtech.com	Product	Bangalore
PMC Sierra	www.pmcs.com	Product	Bangalore
Posedge	www.posedge.com	Product	Hyderabad
QLogic	www.qlogic.com	Product	Bangalore
Qualcomm	www.qualcomm.com	Product	Bangalore/ Hyderabad
Rambus Chip Technologies	www.rambus.com	Product	Bangalore
Rapid Bridge	www.rapid-bridge.com		Bangalore
Renesas	www.renesas.com	Product	Bangalore
RiverSilica Technologies PVT LTD	www.riversilica.com	Services	Bangalore
Saankhya Labs Pvt. Ltd.	www.saankhyalabs.com		Bangalore
Samsung India	www.samsung.com	Product	Bangalore
SanDisk	www.sandisk.in	Product	Bangalore
Sankalp Semiconductors Pvt Ltd	www.sankalpsemi.com	Services	Bangalore
Sasken	www.sasken.com		Bangalore
Semtronics micro systems	www.semtronicsmicrosystems.com	Product	Bangalore
Sibridge Technologies	www.sibridgetech.com		Bangalore
SiCon Design Technologies Pvt. Ltd.	www.sicontech.com	Services	Bangalore
Signalchip Innovations	www.signalchip.com		Bangalore
SmartPlay Technologies	www.smartplayin.com	Services	Bangalore
SMSC	www.smsc.com	Product	Bangalore/ Chennai
SMSilicon	www.siliconindia.com		Hyderabad
Soctronics	www.soctronics.com	Services	Hyderabad
SoftJin Technologies	www.softjin.com		Bangalore
Sonic Chips	www.sonicchips.com		Bangalore
ST Ericsson	www.stericsson.com	Product	Bangalore
STMicroelectronics	www.st.com	Product	Bangalore/ Noida
Sykatia	www.sykatiya.com	Services	Bangalore
Synapse Design	www.synapse-da.com	Services	Bangalore
Synopsys	www.synopsys.com	eda	Bangalore/ Hyderabad/ Noida
Tata Elxsi	www.tataelxsi.com	Services	Bangalore
TCS	www.tcs.com		Bangalore
Tech Vulcan Solutions	www.techvulcan.com	Services	Bangalore
Tensilica	www.tensilica.com	Product	Pune
TESLA Semiconductors			Bangalore
Tessolve Services Pvt. Ltd.	www.tessolve.com		Bangalore
Texas Instruments	www.ti.com	Product	Bangalore
Terminus Circuits	www.terminuscircuits.com	Product	Bangalore
Transwitch	www.transwitch.com	Product	Bangalore
Truechip Solutions	www.truechip.net	Services	Noida
Uniquify	www.uniquify.com		Bangalore
Vayavya Labs Pvt. Ltd	www.vayavyalabs.com		Bangalore
Verification Partner Inc	www.verificationpartner.com	Services	Bangalore
Verific Design Automation	www.verific.com	Product	Bangalore
Virage Logic	www.synopsys.com	Product	Noida
Waferspace Semiconductor	www.waferspace.com	Services	Bangalore
Whizchip Design Technologies Pvt Ltd	www.whizchip.com	Services	Bangalore
Wipro Technologies	www.wipro.com		Bangalore
Xilinx	www.xilinx.com	Product	Hyderabad

Inputs and Outputs of PD (physical design)

Inputs and Outputs at each stage of PD Flow.

Floorplanning:

Inputs:

·    Design Setup

·    Gate Level Netlist

·    Milky way reference Library

·   SDC (Synopsis Design Constraints)

·    TDF (Top Design File)

Outputs:

·         Floorplanned Cell

Checks:

·    Is Macro orientation correct

·    Is placement Legality (i.e. Cell overlaps, cells outside the core boundary ) fine

·   Is Macro placement is according to macro placement guidelines?

·   Placing Macros using Data Flow diagram and by fly-line analysis.

Goal:

·  Goal is to provide continuous area for Standard Cells to be place.

· The Macro plcmt should not lead to Congestion.

Power Planning:

 Inputs:

·         Floor planned Cell

·         Power Budget

·         The top level Engineer may freeze the step , stop, width of Vertical Straps (Because we are designing a block which is going to fit in some chip so the Vertical straps in the chip nd in our block should match, dats the reason In Block level design the top engineer gives us the Vertical straps constraints) {M6pwr.tcl}

Outputs:

·         Power Mesh is Synthesized with IR Drop less than 5 % {VDD+VSS}

·         Floor Planned Cell with Power Mesh

            Checks:

· Check whether u have met the Required IR Drop

· Verify PG connections to check for floating shapes or floating pins  { Power DRC’s }

·Check whether the Placement Legality is fine.

 Goal:

·To meet the Required IR Drop.

If not std cells will not get required power.

 Placement:

 Inputs:

· Floor planned Cell

· Constraints like don’t touch cells (might be already written in SDC ) if not u need to give the cells which u don’t want them to be removed during placement optimization.

· Skew file {in second iteration to meet Timing violations by adding USEFUL SKEW}

Pre requisites for Placement:

·         First of all there should be continuous area for standard cells and the power n/w should be synthesized with the acceptable IR drop.

·         
Checks:

· Check the timing Reports nd analyze them

· Check the Placement Legality

· Check for Global Route Congestion

· Is Std cell Placement Utilization Ok..???

Goal:

· Trying to meet as many setup vio’s as psble.

· Should have acceptable std cell utlzt.

· Should be Congestion Free.

Clock Tree Synthesis:

Inputs:

· Placed Cell

· CTS Constraints

· Non Default Routing Rules {NDR , Bcoz during clock signal (routingclock_route.tcl)Clock nets are largely pruned to Cross Talk effect }

Goal:

·To Balance Insertion Delay

· To make Skew Zero.

For this we this reason we will need to synthesize the clock tree

·After CTS you should meet all the Hold Vio’s.

Checks:

· IS Skew is minimum and Insertion delay balanced.

·IS Timing {Especially Hold} met, if not why?

· If there are timing violations are all the constraints constrained properly.{like not defining false paths, asynchronous paths, multicycle paths}.

· IS std Cell Utilization acceptable at this stage

· Check for Global Route Congestion

· Check for Placement Legality.

digital design interview questions.

# Have you studied buses? What types?
Ans: 1. Processor-Memory Bus, I/O Bus, System Bus, Backplane Bus.

# Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
Ans: A method of executing a sequence of instructions in a single processor so that subsequent instructions in the sequence can begin execution before previous instructions complete execution.

5 Stages:
1. fetch instructions from memory
2. read registers and decode the instruction
3. execute the instruction or calculate an address
4. access an operand in data memory
5. write the result into a register

Latency: It's the amount of time between when the instruction is issued and when it completes. 6 Clock Cycles.
Throughput: The number of instructions that complete in a span of time.

# How many bit combinations are there in a byte?
Ans: 256

# For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
Ans:

# Explain the operation considering a two processor computer system with a cache for each processor.
Ans:

# What are the main issues associated with multiprocessor caches and how might you solve them?
Ans:

# Explain the difference between write through and write back cache.

# Are you familiar with the term MESI?

# Are you familiar with the term snooping? Ans: Looking into a packet to obtain information. Usuall used to verify data at the output a logic core with inbuilt snoopers.

# Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
Ans:

# In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
Ans:

# You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
Ans:

# What is the difference between = and == in C? Ans: Assignment and Equality operators.

# Are you familiar with VHDL and/or Verilog?
Ans:

# What types of CMOS memories have you designed? What were their size? Speed? Ans: SRAM, 10Kbits, 50 Mhz.

# What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
Ans:

# What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Ans:

# Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?
Ans:

# What types of high speed CMOS circuits have you designed? Ans: FF's and Latch based Fast Mutipliers.

# What transistor level design tools are you proficient with? What types of designs were they used on? Ans: PSPICE, MAGIC layout system, CMOS mutiplier chip, 0.8 u tech.

# What products have you designed which have entered high volume production?
Ans: TOE.

# What was your role in the silicon evaluation/product ramp? What tools did you use? Ans:

# If not into production, how far did you follow the design and why did not you see it into production? Ans:

# Explain how a MOSFET works. Ans:

# Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width © considering Channel Length Modulation Ans:

# Explain the various MOSFET Capacitances & their significance Ans:

# Draw a CMOS Inverter. Explain its transfer characteristics
Ans:

# Explain sizing of the inverter
Ans:

# How do you size NMOS and PMOS transistors to increase the threshold voltage?
Ans:

# What is Noise Margin? Explain the procedure to determine Noise Margin?
Ans:

# Give the expression for CMOS switching power dissipation.
Ans:

# What is Body Effect?
Ans:

# Describe the various effects of scaling?
Ans:

# Give the expression for calculating Delay in CMOS circuit Ans: Tp = (tphl+tplh)/2, where tphl = 0.69 Req C & tplh = 0.69 Req C where C is the external capacitance made up of the diffusion capactiances of the drain and the fanout capacitance of the gates, Req is the equivalent resistance which could be either integrated if we are actually talking about in the resistive region or can be calculated in the saturation region.

# What happens to delay if you increase load capacitance? Ans: If the load capacitance increases that means that the internal difusion capacitance or the fanout of the gate is increasing. i.e. resistance of the gate also increases so increasing the capacitance increasing does not make much of the difference.

# What happens to delay if we include a resistance at the output of a CMOS circuit? Ans: cause power dissipiation.

# What are the limitations in increasing the power supply to reduce delay? Ans: Increase in Dynamic Power dissipation

# How does Resistance of the metal lines vary with increasing thickness and increasing length? Ans: Resistance is directly propotional to length and inversly propotional to area, hence higher metals have lesser resistance and Increasing L increases the resistance.

# What happens if we increase the number of contacts or via from one metal layer to the next? Ans: Increase in contact resistance.

# Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Ans:

# Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
Ans:

# Draw the stick diagram of a NOR gate. Optimize it.
Ans:

# For CMOS logic, give the various techniques you know to minimize power consumption
Ans:

# What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Ans:

# Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Ans:for optimized performance.

# In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Ans:

# Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Ans:

# Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Ans:

# Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Ans: NMOS passes clean zero and a bad one while PMOS passes clean 1 and bad zero(Ref: Kamran)

# For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Ans:

# Draw a 6-T SRAM Cell and explain the Read and Write operations
Ans:

# Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
Ans:

# What happens if we use an Inverter instead of the Differential Sense Amplifier?

Ans:

# Draw the SRAM Write Circuitry?

Ans:

# Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

Ans:

# How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?

Ans:

# What’s the critical path in a SRAM?

Ans:

# Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

Ans:

# Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers?

Ans:

# In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

Ans:

# How can you model a SRAM at RTL Level?

Ans:

# What’s the difference between Testing & Verification?

Ans:

# For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)?

Ans:

# What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

Ans:latch-up: A latchup is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure, which then acts as a short circuit, disrupting proper functioning of the part and possibly even leading to its destruction due to over current.

 Tap cells gives reverse bias to the n-well and p-well . This is to avoid latchup.

Tap cells are used to spread the substrate potential around the area to keep the Vt levels as predicted.